Field
Aspects of the present disclosure relate generally to delay circuits, and more particularly, to programmable delay circuits.
Background
Programmable delay circuits are increasingly being employed in a wide range of low power, low latency applications including Double Data Date (DDR) systems. For example, programmable delay circuits may be used in a DDR system to adjust the timing of data signals in order to compensate for skew between the data signals (e.g., due to mismatches in the lengths of their signal paths). In another example, a programmable delay circuit may be used to adjust the timing of a data strobe signal in order to center the data strobe signal in the data eye of a data signal.